A static random access memory (SRAM) is a volatile-type memory and include many memory cells arranged in an array. Each memory cell includes a latch portion having four cross-coupled transistors and two selection transistors for permitting the memory cell to be selectively addressed.
A nonvolatile-type memory in which the transistors in the latch portion of the otherwise volatile SRAM design are replaced with ferroelectric field effect transistors (FeFETs) is known. However, in such a nonvolatile memory, erasing data is performed via a holding node of the memory cell and thus, erroneous writing/erasing may occur in memory cells which are not intended to be erased in the erasing process.